1. Field of the Invention
The present invention relates to a power on reset circuit for producing a reset signal for initializing an integrated circuit when a power supply is turned on.
2. Related Background Art
Integrated circuits, such as electronic calculators and clocks, must be initialized when a power supply is turned on. In order to detect the turning ON of the power supply to produce pulses to set the state of an integrated circuit to be a predetermined state, a power on reset circuit is used.
FIG. 5 is a circuit diagram of a conventional power on reset circuit of this type. In this diagram, the source of a P-channel FET P1 is connected to a power supply voltage Vcc terminal. To the drain of the P-channel FET P1, one end of a circuit of serially-connected resistors R1 and R2 for dividing a potential is connected. The other end of the serially-connected circuit is connected to an ground terminal. The gate of an N-channel FET N1 is connected to the mutual connection of the resistors R1 and R2, i.e., to a node A. The source of the N-channel FET N1 is connected to the ground terminal. The source of a P-channel FET P2 is connected to the power supply voltage Vcc terminal. To the drain of the P-channel FET P2, the drain of an N-channel FET N2 is connected. The source of the N-channel FET N2 is connected to the ground terminal. The drain of the N-channel FET N1 is connected to the connection of the drains of the P-channel FET P2 and the N-channel FET N2, i.e., to a node B. The input terminal of an inverter INV1 is also connected to the node B. The output terminal of the inverter INV1 is connected to the gates of the P-channel FET P2 and the N-channel FET N2 as well as to the gate of the P-channel FET P1. From the output terminal of the inverter INV1, a reset signal R is outputted.
Also referring to FIGS. 6 and 7, the operation of this power on reset circuit will be described below.
In this power on reset circuit, it is presupposed that the reset signal R is in an ground point level, i.e., in a reset on state, in the initial state in which the power supply is turned on. When a power supply voltage Vcc rises with time, the P-channel FET P1 for receiving the reset signal R as a gate input is changed to an ON state to allow a through current I1 to flow through the circuit of serially-connected resistors R1 and R2. Therefore, the level of the node A, the potential of which is determined by the ratio of the resistors R1 and R2, also gradually rises in accordance with the rise of the power supply voltage Vcc. When the potential reaches a predetermined value, the N-channel FET N1 is changed to an ON state. When the N-channel FET N1 is changed to the ON state, a current I2 is allowed to flow through the P-channel FET P2 for holding the level of the reset signal R.
When the power supply voltage Vcc further rises so that the driving force of the N-channel FET N1 reaches a point exceeding the P-channel FET P2, i.e., a Vth in FIG. 6, the reset signal R is inverted to the level of the power supply voltage Vcc by means of the inverter INV1 which receives the potential of the node B, and the reset is canceled after time t1, so that the level is held by the N-channel FET N2.
In the conventional power on reset circuit shown in FIG. 5, there are some cases where the initial state of the reset signal R, in which the power supply is turned on, follows the rise of the power supply voltage Vcc under the influence of the parasitic capacity, which is parasitic on the respective elements, and under the influence of the residual electric charge as shown in FIG. 7. In this case, since the circuit is held in the stable state, no reset signal is outputted, so that the malfunction of the system occurs.